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copyright ? 2010, kt micro, inc. 1 figure 1: system diagram ? description the KT0830EG is a high-quality monolithic digital fm receiver designed to playback high-fidelity fm broadcasting signals under various conditions. the KT0830EG offers a true single-chip fm radio solution. there are no external filter s or frequency-tuning devices thanks to a proprietary digital low-if architecture, a fully- integrated lna, automatic gain control (agc), high- performance adcs, high-quality analog and digital filters, and an on-chip low-noise self-t uning vco. the on-chip high- fidelity class-ab driver further eliminates the need for any external audio amplifiers and can drive stereo headphones directly. the on-chip ldo regulator allows the chip to operate with power supply ranging from 2.0v to 3.6v consuming merely 19ma in full operation mode and less than 10ua when standby ? greatly extending the battery life. the small footprint, high integrat ion level and great flexibility make KT0830EG for any standalone fm radio applications. KT0830EG stereo fm receiver radio-on-a-chip? ? features fully compatible with kt0830e excellent radio reception with short antenna 32.768khz and 38khz crystal support variable reference clock support including 32.768 khz/7.6mhz/12mhz/24mhz excellent tuning experience with built in snr meter and rssi low-cost true single-chip fm radio solution single-chip low if fm receiver direct band, volume, frequency selection digital fm demodulator digital stereo processor low-noise pll with integrated vco extended fm band support (64-109mhz) integrated class ab headphone driver high fidelity snr: 64db thd: <0.3% high sensitivity: -106dbm low supply current 19ma (operating), 1ua (power-down) high driving capability drive up to 16 ohm load (single-sided) automatic frequency control (afc) automatic gain control (agc) anti-pop circuit 16-pin sop package ? applications single chip fm radio used in pmp, boom box, sporting devices, medical devices and etc rev. 1.2 information furnished by kt micro is believed to be accurate and reliable. however, no responsibility is assumed by kt micro for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of kt micro, inc. ???? ? www.sbdsemi.cn ? 086-0755-81753689/83340989 ? 13642365547 ( ) email: yangbin7575@1633.com ???????????? free datasheet http:///
copyright ? 2010, kt micro, inc. 2 KT0830EG table of content section ....................................................................................................................... ................... ....... page 1 electrical specification ........................ .......................... .......................... .......................... .................... 3 2 pin list ...................................................................................................................... ............................. 4 3 functional description ........................................................................................................ .................. 6 3.1 overview ...................................................................................................................... ......... 6 3.2 fm receiver ................... ......................... .......................... .......................... ................... ....... 6 3.3 digital signal processing ..................................................................................................... . 6 3.4 stereo dac, audio filter and driver .......................... .......................... ................... ............. 7 3.5 seek/tune ..................................................................................................................... .... 7 3.6 power on sequence.............................................................................................................. .. 8 3.7 reference clock ............................................................................................................... ..... 8 4 control interface- i2c ........................ .......................... .......................... ............................ .................. 8 5 register map ..................... ......................... .................... ................... .................... ......... ...................... 10 5.1 device id register (reg 0x00) ........................................................................................... 11 5.2 chip id (reg 0x01) ............................................................................................................ 11 5.3 seek configuration (reg 0x02) ......... .................................................................................. 11 5.4 tune register (reg 0x03) ............... .................................................................................. 11 5.5 volume control register (reg 0x04) .............................................................................. 12 5.6 dsp configuration register a (reg 0x 05) ......................................................................... 13 5.7 lo synthesizer configuration a (reg 0x0a) ................... ........................ .......................... 13 5.8 system configuration register (reg 0x0f) ........................................................................ 14 5.9 status register a (reg 0x12) ...... ........................................................................................ 15 5.10 status register b (reg 0x13) ...... ........................................................................................ 15 5.11 . status register c (reg 0x14) ............................................................................................ 16 5.12 status register d (reg 0x15) ...... ........................................................................................ 16 5.13 snr register (reg 0x1f) .................. .................................................................................. 16 5.14 seekth register (reg 0x20) ............................................................................................ 16 5.15 softmute register (reg 0x21) ............................................................................................. 16 5.16 clock register (reg 0x23) .................................................................................................. 17 6 application circuit ........................................................................................................... .................... 18 7 package ....................................................................................................................... .......................... 20 8 order information ............................................................................................................. ................. 20 9 revision history .............................................................................................................. .................... 21 10 contact information ........................................................................................................... ................ 21 ???? ? www.sbdsemi.cn ? 086-0755-81753689/83340989 ? 13642365547 ( ) email: yangbin7575@1633.com ???????????? free datasheet http:///
copyright ? 2010, kt micro, inc. 3 KT0830EG 1 electrical specification table 1: operation condition parameter symbol operating condition min typ max units power supply vdd relative to vss 2.0 3.3 3.6 v operating temp tj junction temperature -20 50 110 c table 2: dc characteristics parameter symbol test/operating condition min typ max units current consumption i a - 19 - ma standby current i apd 6 10 a power-down current i pd 1 3 a table 3: fm receiver characteristics (unless otherwise noted tj = -20~110 o c, vdd =2.0v to 3.6v) parameter symbol test/operating condition min typ max units fm frequency range f r x 64 109 mhz sensitivity 1,2,3 sen (s+n)/n=26db 2.2 3.5 uvemf input referred 3 rd order intermodulation production 4,5 iip3 87 dbuve mf adjacent channel selectivity 200khz 40 51 db alternate channel selectivity 400khz 50 70 db image rejection radio 35 db am suppression 50 db rclk frequency 32 32.768 26000 khz rclk frequency range 8 -100 100 ppm audio output voltage 1,2,3,4 32ohm load 68 70 72 mv rms audio band limits 1,2,4 3db 30 15k hz audio stereo separation 1,4,6 35 db audio stereo s/n 1,4,6,7 64 db audio thd 1,2,4,6 0.3 % audio common mode voltage 0.7 v audio output load resistance r l single-ended 16 ? seek/tune time (effective channel) 50 ms/ch power-up time 380 ms notes: 1. fmod=1khz, 75us de-emphasis 2. mono=1 3. f=22.5khz 4. v emf =1mv, frx=70mhz~110mhz 5. agcd=1 6. f=75khz 7. volume<3:0>=1111 8. the supported rclk frequency is not continuous. please refer to application notes. ???? ? www.sbdsemi.cn ? 086-0755-81753689/83340989 ? 13642365547 ( ) email: yangbin7575@1633.com ???????????? free datasheet http:///
copyright ? 2010, kt micro, inc. 4 KT0830EG 2 pin list a 16-pin sop package is used. the chip io pin-out is listed in table 4. table 4 pin-out pin index name i/o type function 1 vdd power 2.0v ? 3.6v power supply 2 gnd ground ground 3 gnd ground ground 4 sclk digital input i2c clock input. 5 sdio digital io i2c data input/output 6 lout analog output left channel output with 16 ohm driving capability. 7 rout analog output right channel output with 16 ohm driving capability. 8 gnd ground ground 9 vdd power 2.0v ? 3.6v power supply. 10 xi/rclk analog io 32.768khz crystal input or 32.768khz external reference clock input. 11 xo analog io 32.768khz crystal input 12 power_on digital input high for normal operating mode and low for standby mode. 13 n.c. n.c. no connection 14 gnd ground ground 15 rfinp analog input rf signal input. external ac coupling cap is not required 16 gnd ground ground figure 2: pin out ???? ? www.sbdsemi.cn ? 086-0755-81753689/83340989 ? 13642365547 ( ) email: yangbin7575@1633.com ???????????? free datasheet http:///
copyright ? 2010, kt micro, inc. 5 KT0830EG table 5: i/o pin configuration pad schematic sclk sdio rfinp poweron ???? ? www.sbdsemi.cn ? 086-0755-81753689/83340989 ? 13642365547 ( ) email: yangbin7575@1633.com ???????????? free datasheet http:///
copyright ? 2010, kt micro, inc. 6 KT0830EG 3 functional description 3.1 overview the KT0830EG offers a true single-chip fm radio solution by virtually eliminating all the external components. there are no exte rnal filters or freq uency-tuning devices thanks to a proprietary digital low-if architecture, a fully-integrated lna, automatic gain control (agc), high-performance adcs , high-quality analog and digital filters, and an on-chip low-noise self-tuning vco. the on-chip high-fidelity class-ab driver further eliminates the need for any external audio amplifiers and can drive stereo headphones directly. 3.2 fm receiver a high performance digital-if structure receiver is used in KT0830EG to convert rf signal to if signal. the received if signal is digitized by a high resolution analog to digital converter (adc) and all of the following signal processing including channel filtering, fm demodulation and stereo decoding is performed digitally. in order to improve the dynamic range of the rf signal, an automatic gain control (agc) loop is used together with the lo w noise amplifier (lna). 3.3 digital signal processing 3.3.1 stereo decoder the digitized if signal is fed to the fm demodulator which demodulates the signal and outputs a digital multiplexed (mpx) signa l consisting of l+r audio, l-r audio, 19khz pilot tone. the left channel signal and the right channel signal can be extracted from the mpx signal by simply adding and subtracting the l+r signal and l-r signal. the spectrum diagram is shown in figure 3. figure 3: spectrum diagram of the mpx signal ???? ? www.sbdsemi.cn ? 086-0755-81753689/83340989 ? 13642365547 ( ) email: yangbin7575@1633.com ???????????? free datasheet http:///
copyright ? 2010, kt micro, inc. 7 KT0830EG 3.3.2 mute KT0830EG can be hard muted by setting volume to 0 and the output of the audio signal is set to the common mode voltage. there is also a soft mute feature that is enabled by setting smute_b to 0. in this mode, the audio volume is gradually attenuated when the signal reception is bad (i.e. when the rssi or snr, which is determin ed by reg smmd, is below a certain level as defined by smth<2:0>.) the reg volumet<3:0> sets the lowest volume that the internal state machine can reach. the attenuation attack rate and depth can be configured through smuter<1:0> and smutea<1:0>, respectively. 3.3.3 stereo / mono blending in order to provide a comfortable listening experience, KT0830EG blends the stereo signal with mono signal gradually when in weak reception. the signal level range over which the blending occurs is set by blndadj<1:0>. the blending is disabled when dblnd is set to 1 . mono playback mode can also be forced by setting the mono to 1. 3.3.4 bass boosting KT0830EG provides a digital audio enhancement feature, bass boosting. the gain of the bass boost can be programmed through bass<1:0> (reg0x04<9:8>). with bass<1:0>=00, this feature is disabled. 3.4 stereo dac, audi o filter and driver two high-quality single-bit ? audio digital to analog converters (dac) are integrated along with high-fidelity analog audio filters and class ab drivers. headphones or speakers with impedance as low as 16ohms can be directly driven without external audio drivers. an integrat ed anti-pop circuit eliminates the click- and-pop sound during power up and power down. 3.5 seek/tune the fully integrated lo synthesizer supports wide band operation from 64mhz to 110mhz . the chip begins to directly tune to a channel when the register tune is set to 1. the channel frequency can be programmed and tuned by setting chan<9:0> which is defined as freq(mhz) = 50 khz chan<9:0> + 64 mhz the seeking process is star ted by setting seek to ?1?. two built-in seek methods are available, which are distinguished by setting seek_sel. seeking direction is determined by seekdir. the band edges are determined by band<1:0> and the seek step is set by space<1:0>. KT0830EG automatically seeks and tunes to the first satisfying station. if no qualified chan nel is found, the fm receiver returns to the original channel and sf/bl bit is set to ?1?. when seekmd is set to 0. alternatively, if seekmd is set to 1 and no qualified channel is found, the chip stops at the band edge while setting sf/bl bit to 1. when autotune bit is set to 1, the chip will automatically tune to the found channel, ot herwise, the chip will remain mute after ???? ? www.sbdsemi.cn ? 086-0755-81753689/83340989 ? 13642365547 ( ) email: yangbin7575@1633.com ???????????? free datasheet http:///
copyright ? 2010, kt micro, inc. 8 KT0830EG seek is completed. during the seeking, the current channel can be read out from readch<9:0> bits. refer to application notes for more information. 3.6 power on sequence KT0830EG is powered up by pulling the po wer_on pin to high. or leaving this pin not connection. no external power-on reset circuit is required. one needs to wait for 400ms before he/she can configure the chip through the serial interface. 3.7 reference clock the kt0810g support variable reference clock frequencies, such as 32.768khz, 7.6mhz, 12mhz, 13mhz, 24 mhz, 26mhz and etc. the built-in crystal oscillator also supports 32.768khz and 38khz crystal. please refer to application notes for more information about setting different reference clock. 4 control interface- i2c i2c bus mode uses sclk and sdio to transfer data. the device always drives data to sdio at the falling edge of sclk and captures data from sdio at the rising edge of sclk. the device acknowledges the external controller by driving sdio low at the falling edge of sclk. data tran sfer always be gins with start condi tion and ends with stop condition. the external controller can read/write one 16-bits data at the specified address or read/write desired number of registers data continuously from the specified address till when stop condition is occurred. for write operations, external controller s hould send command & data in the following sequence: start condition -> 7 bit chip address and write command (?0?) -> 8 bit register address n -> write data n [15:8] -> write data n [7:0] -> write data n+1 [15:8] -> write data n+1 [7:0] -> ?? -> stop condition. for read operations, external controller should send command & data in the following sequence: start condition -> 7 bit chip address and write command (?0?) -> 8 bit register address n -> 7 bit chip address and read command (?1?) , th en device will send read data n [15:8] -> read data n [7:0] -> read data n+1 [15:8] -> read data n+1 [7:0] - > ?? till stop condition. table 6 : i2c interface protocol random register write procedure s 0 1 1 x 1 1 1 w a a a ap 7 bit chip address register address write data [15:8] write data [7:0] acknowledge acknowledg e acknowledge start condition write command stop condition ???? ? www.sbdsemi.cn ? 086-0755-81753689/83340989 ? 13642365547 ( ) email: yangbin7575@1633.com ???????????? free datasheet http:///
copyright ? 2010, kt micro, inc. 9 KT0830EG random register read procedure s 0 1 1 x 1 1 1 w a as011x111 r a ? a ? a p 7 bit chip address register address 7 bit chip address read data [15:8] read data [7:0] acknowledge a cknowledge acknowledge start condition write command read command n o acknowledge stop condition note: the data bits in gray color are sent by KT0830EG 1-7 8 9 1-7 8 9 1-7 8 9 sdio sclk s p chip addr ack reg addr ack data ack r/w figure 4: i2c interface timing diagram ???? ? www.sbdsemi.cn ? 086-0755-81753689/83340989 ? 13642365547 ( ) email: yangbin7575@1633.com ???????????? free datasheet http:///
copyright ? 2010, kt micro, inc. 10 KT0830EG 5 register map regnamed15d14d13d12d11d10d9d8d7d6d5d4d3d2d1d0 0 0 h devi c e 01h chipid 02h seek seek seekdir 03h tune tune autotun e 04h volume smute_b mute_b 0 5 h dspc fg a mono de dblnd 09h rfcfg 0ah locfga afcd hlsi 0fh syscfg intlvl sftrst stcien stdby seekmd seek_sel 12h statusa xtal_ok stc sf/bl pll_ld lo_ld 13h statusb 14h statusc 15h statusd 1dh antenna 1fh snr 20h seekth 21h softmute smmd smth<2> 23h clock rclk_en lrswap ant_tun e_en seekth<4:0> smuter<1:0> smutea<1:0> fm_band<1:0> bass<1:0> smth<1:0> volume<3:0> chan<9>0> afc_deltaf<5:0> space<1:0> afc_deltaf<7:0> afcrange<2:0> st<1:0> gpio1<1:0> rssi<4:0> readchanchan<9:0> gpio3<1:0> gpio2<1:0> mfgid<15:0> dev<15:0> adv_seekth_high adv_seekth_low anttyp<1:0> blndadj<1:0> ref_clk<3:0> snrth<7:0> snr<7:0> ???? ? www.sbdsemi.cn ? 086-0755-81753689/83340989 ? 13642365547 ( ) email: yangbin7575@1633.com ???????????? free datasheet http:///
copyright ? 2010, kt micro, inc. 11 KT0830EG the register bank stores channel frequency codes, calibration parameters, operation status, mode and power controls, which can be accessed by the internal digital controller, state machines and external micro contro llers through the serial interface. all registers are 16 bits wide. control logics are active high unless specifically noted. all the registers are automatically set to default values after the chip is powered-on or reset. 5.1 device id register (reg 0x00) bit symbol access default functional description 15:0 mfgid<15:0> r 0xb002 manufacturer id 5.2 chip id (reg 0x01) bit symbol access default functional description 15:0 dev<15:0> r 0x0440 part number 0x0440=fm receiver 5.3 seek configur ation (reg 0x02) bit symbol access defaul t functional description 15 seek rw 0 seek enable 0 = disable 1 = enable 14 seekdir rw 0 seek direction 0 = seek down 1 = seek up 13:12 reserved rw 10 reserved 11:7 seekth<4:0> rw 00110 seek threshold 00000 = most sensitive 11111 = least sensitive 6 reserved 0 reserved 5:4 fm_band<1:0> rw 00 band selection 00 = 87-108mhz (usa, europe) 01 = 76-108mhz (japan wide band) 10 = 76-90mhz (japan). 11 = reserved 3:2 space<1:0> rw 00 channel spacing 00 = 200khz (us, europe) 01 = 100khz (europe, japan) 10 = 50khz 1:0 reserved 11 reserved 5.4 tune register (reg 0x03) bit symbol access default functional description ???? ? www.sbdsemi.cn ? 086-0755-81753689/83340989 ? 13642365547 ( ) email: yangbin7575@1633.com ???????????? free datasheet http:///
copyright ? 2010, kt micro, inc. 12 KT0830EG 15 tune rw 0 tune enable 0 = disable 1 = enable 14:13 reserved rw 00 12 autotune rw 1 automatic tune control 0 = will not tune after a successful seek until a separated tune command is received from the control interface 1 = automatically starts tune process after seek 11:10 reserved rw 10 9:0 chan<9:0> rw 1cc tune channel value 5.5 volume control re gister (reg 0x04) bit symbol access defaul t functional description 15 smute_b rw 1 softmute disable 0 = softmute enable 1 = softmute disable 14 mute_b rw 0 hard mute disable 0 = mute enable 1 = mute disable 13:12 smuter<1:0> rw 00 softmute attack/recover rate 0 = slowest 01 = fastest (rssi mode only) 10 = fast 11 = slow 11:10 smutea<1:0> rw 00 softmute attenuation 00 = strong 01 = strongest 10 = weak 11 = weakest 9:8 bass<1:0> rw 00 bass boost effect mode selection 00 = disable 01 = low 10 = med 11 = high 7:6 reserved 00 5:4 smth<1:0> rw 10 soft mute start level together with smth<2> in reg0x21 000 = lowest ?? 111 = highest ???? ? www.sbdsemi.cn ? 086-0755-81753689/83340989 ? 13642365547 ( ) email: yangbin7575@1633.com ???????????? free datasheet http:///
copyright ? 2010, kt micro, inc. 13 KT0830EG 3:0 volume<3:0> rw 0111 volume control 0000 = mute 0001 = -42dbfs 0010 = -39dbfs ?? ??. 1110 = -3dbfs 1111 = fs 5.6 dsp configuration register a (reg 0x05) bit symbol access default functional description 15 mono rw 0 mono select 0 = stereo 1 = force mono 14:12 reserved rw 101 reserved 11 de rw 0 de-emphasis 0 = 75us. used in usa. 1 = 50us. used in europe, australia, japan. 10 reserved rw 0 9:8 blndadj<1:0> rw 00 stereo/mono blend start level 00 = high 01 = highest 10 = lowest 11 = low note: write 00 explicitly even if 00 is the default value. 7:6 reserved rw 00 reserved 5 dblnd rw 0 blend disable 0 = blend enable 1 = blend disable 4:0 reserved 00000 reserved 5.7 lo synthesizer configuration a (reg 0x0a) bit symbol access default functional description 15 reserved rw 0 14:12 afcrange<2:0> rw 000 afc correction range 000 = 12khz 001 = 15khz 010 = 14khz 011 = 17khz 100 = 16khz 101 = 19khz 110 = 22khz 111 = 25khz 11:9 reserved rw 000 ???? ? www.sbdsemi.cn ? 086-0755-81753689/83340989 ? 13642365547 ( ) email: yangbin7575@1633.com ???????????? free datasheet http:///
copyright ? 2010, kt micro, inc. 14 KT0830EG 8 afcd rw 1 afc disable control bit 0 = afc enable 1 = afc disable 7 reserved rw 0 6 hlsi rw 0 high side or low side injection 1 = high side injection 0 = low side injection 5:0 reserved r 000000 reserved 5.8 system configuratio n register (reg 0x0f) bit symbol access default functional description 15 intlvl rw 1 interrupt level control (gpio2) 0 = low level interrupt 1 = high level interrupt 14 sftrst rw 0 soft reset bit 0 = normal operation 1 = soft reset 13 stcien rw 0 seek/tune complete interrupt enable 0 = disable interrupt 1 = enable interrupt 12 stdby rw 0 standby mode (see version notes) 0 = disable 1 = enable 11 reserved rw 1 reserved 10 seekmd rw 0 seek mode selection 0 = cycling seek 1 = stop at the band edge. 9:7 reserved rw 100 6 seek_sel rw 0 seek method selection 0 = traditional method 1 = advanced method 5:4 gpio3<1:0> rw 00 general purpose i/o 3 00 = high impedance 01 = mono/stereo indicator (st). gpio3 = high for stereo gpio3 = low for mono 10 = low 11 = high 3:2 gpio2<1:0> rw 00 general purpose i/o 2 00 = high impedance 01 = stc interr upt/rds group synchronization interrupt/ 10 = low 11 = high ???? ? www.sbdsemi.cn ? 086-0755-81753689/83340989 ? 13642365547 ( ) email: yangbin7575@1633.com ???????????? free datasheet http:///
copyright ? 2010, kt micro, inc. 15 KT0830EG setting stcien=1 will generate a high level interrupt on gpio2 when the stc bit is set. setting rdsien=1 will generate a high level interrupt on gpio2 when rds is synchronized. 1:0 gpio1<1:0> rw 00 general purpose i/o 1 00 = high impedance 01 = reserved 10 = low 11 = high 5.9 status register a (reg 0x12) bit symbol access default functional description 15 xtal_ok r 0 crystal ready indictor 0 = not ready 1= crystal is ok 14 stc rw 0 seek/tune complete 0 = not complete 1 = complete the status can be cleared manually 13 sf/bl rw 0 seek fail or band limit 0 = seek successful 1 = seek failure 12 reserved r 0 11 pll_lock r 1 system pll ready indicator 0 = not ready 1 = system pll ready 10 lo_lock r 1 lo synthesizer ready indicator 0 = not ready 1 = ready 9:8 st<1:0> r 00 stereo indicator 11 = stereo other= mono 7:3 rssi<4:0> r 00000 rssi value indicator rssi indication range is from -100dbm to -7dbm with 3db resolution, where 00000 means minimum level and 11111 means maximum level. 2:0 reserved r 000 reserved 5.10 status register b (reg 0x13) bit symbol access default functional description 15:10 reserved r 000000 reserved 9:0 readchan<9:0> r 0 the current channel readchan<9:0> provides the ???? ? www.sbdsemi.cn ? 086-0755-81753689/83340989 ? 13642365547 ( ) email: yangbin7575@1633.com ???????????? free datasheet http:///
copyright ? 2010, kt micro, inc. 16 KT0830EG current channel during seek or after a seek or tune operation is completed 5.11 . status register c (reg 0x14) bit symbol access default functional description 15:6 reserved r 0000000000 reserved 5:0 afc_deltaf_5767<5:0> r 000000 frequency difference between chan and received signal, calculated by afc block in two?s complement format . range is -31 to +31. unit is khz. this register is valid when stc=1 5.12 status register d (reg 0x15) bit symbol access default functional description 15:8 reserved r 00000000 reserved 7:0 afc_deltaf<7:0> r 00000000 frequency difference between chan and received signal, calculated by afc block in two?s complement format . range is -127 to +127. unit is khz. this register is valid when stc=1 5.13 antenna register (reg 0x1d) bit symbol access default functional description 15:0 reserved 5.14 snr register (reg 0x1f) bit symbol access default functional description 15:8 snrth<7:0> rw 0x00 snr threshold for traditional seek mode 7:0 snr<7:0> r 0x00 snr value of current channel 0x00 = worst ?? 0xff = best 5.15 seekth register (reg 0x20) bit symbol access defaul t functional description 15:8 adv_seekth_high rw 0x14 high threshold for advanced seek mode 7:0 adv_seekth_low rw 0x19 low threshold for advanced seek mode 5.16 softmute register (reg 0x21) bit symbol access default functional description ???? ? www.sbdsemi.cn ? 086-0755-81753689/83340989 ? 13642365547 ( ) email: yangbin7575@1633.com ???????????? free datasheet http:///
copyright ? 2010, kt micro, inc. 17 KT0830EG 15:7 reserved rw 000100000 reserved 6 smmd rw 0 softmute mode selection 0 = rssi 1 = snr 5:4 reserved rw 01 reserved 3 smth<2> rw 0 softmute threshold msb, together with smth<1:0> in reg0x04 000 = lowest 001 = ? 111 = highest 2:0 reserved rw 010 reserved 5.17 clock register (reg 0x23) bit symbol access default functional description 15:13 reserved rw 000 reserved 12 rclk_en rw 0 reference clock enable 0 = crystal 1 = reference clock 11:8 ref_clk<3:0> rw 0000 reference clock selection 0000 = 32.768khz 0001 = 6.5mhz 0010 = 7.6mhz 0011 = 12mhz 0100 = 13mhz 0101 = 15.2mhz 0110 = 19.2mhz 0111 = 24mhz 1000 = 26mhz 7:5 reserved rw 000 reserved 4 lrswap rw 0 swap left and right audio channels 0 = don?t swap 1 = swap 3:0 reserved rw 0 reserved ???? ? www.sbdsemi.cn ? 086-0755-81753689/83340989 ? 13642365547 ( ) email: yangbin7575@1633.com ???????????? free datasheet http:///
copyright ? 2010, kt micro, inc. 18 KT0830EG 6 application circuit sclk sdio lout rout vdd rfinp power_on xo xi/rclk gnd vdd gnd gnd n.c 1 2 3 4 5 6 7 89 10 11 12 13 14 15 16 kt0830e g c2 c3 from battery c1 external clock input gnd gnd figure 5: typical application circuit (reference clock) note the decoupling c1 should be close to pin 8 and pin 9 table 7: bill of material components value/description suppliers c1 supply decoupling capacitor, 0.1uf c2,c3 ac decoupling capacitor, 100uf ???? ? www.sbdsemi.cn ? 086-0755-81753689/83340989 ? 13642365547 ( ) email: yangbin7575@1633.com ???????????? free datasheet http:///
copyright ? 2010, kt micro, inc. 19 KT0830EG sclk sdio lout rout vdd rfinp power_on xo xi/ rclk gnd vdd gnd gnd n.c 1 2 3 4 5 6 7 89 10 11 12 13 14 15 16 KT0830EG c2 c3 from battery c1 gnd gnd c4 c5 r1 (recommended) y1 figure 6: typical application circuit (crystal) note the decoupling c1 should be close to pin 8 and pin 9 table 8: bill of material components value/description suppliers c1 supply decoupling capacitor, 0.1uf c2,c3 ac decoupling capacitor, 100uf c4,c5 capacitor, 24pf y1 crystal, 32.768khz r1 resistor, 10mohm ???? ? www.sbdsemi.cn ? 086-0755-81753689/83340989 ? 13642365547 ( ) email: yangbin7575@1633.com ???????????? free datasheet http:///
copyright ? 2010, kt micro, inc. 20 KT0830EG 7 package 8 order information part number description package moq KT0830EG 2 nd gen single-chip stereo fm receiver sop-16 5000 ???? ? www.sbdsemi.cn ? 086-0755-81753689/83340989 ? 13642365547 ( ) email: yangbin7575@1633.com ???????????? free datasheet http:///
copyright ? 2010, kt micro, inc. 21 KT0830EG 9 revision history v1.0 official release v1.1 pin 14 and pin 2 v1.2 added figure 7 and table 9 ???? ? www.sbdsemi.cn ? 086-0755-81753689/83340989 ? 13642365547 ( ) email: yangbin7575@1633.com ???????????? ???? ? www.sbdsemi.cn ? 086-0755-81753689/83340989 ???????????? free datasheet http:///

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